The present invention relates generally to synchronization of clock and data signals and, more particularly, to circuits capable of clock and data recovery.
Communication systems may transport large amounts of data at very high data rates. The transportation of data within communication systems may typically be governed by one or more standards that ensure the reliability of data transfer and the integrity of data conveyances. In accordance with such standards, many system components and end user devices of a communication system transport data via serial transmission paths. For example, a variety of Ethernet standards have been developed for serial data transmissions within a communication system at data rates of 10 megabits per second, 100 megabits per second, 1 gigabit per second and beyond. Internally, however, the system components and end user devices of the communication system may process data in a parallel manner. Accordingly, each receiving system component and end user device may be required to receive the serial data and convert the serial data into parallel data without loss of information.
A clock and data recovery (CDR) receiver may be used for accurate recovery of information from high-speed serial transmissions. FIG. 1A is a block diagram of a conventional serializer/deserializer (SERDES) system 10. Referring to FIG. 1A, the SERDES system 10 may include a phase-locked loop (PLL) clock system 16 at a transmitter side, a clock/data recovery (CDR) 18 at a receiver side, and a number of SERDES sets 10-1 to 10-N corresponding to a number of channels 11-1 to 11-N, N being a natural number. The clock system 16, which is common to the SERDES sets 10-1 to 10-N, may provide a system clock based on a reference clock. The CDR 18, which is also common to the SERDES sets 10-1 to 10-N, may provide a clock signal and a recovered system clock. Each of the SERDES sets 10-1 to 10-N may be configured to convert parallel data to serial data and vice versa in one of the corresponding channels 11-1 to 11-N.
In operation, as an example of the SERDES set 10-1, data to be transmitted from a transmitter that include bit 0 to bit 7, denoted as TX [7:0], are sent to an encoder 12. The encoder 12 may include a “pseudo random binary system” (PRBS)-format encoder based on an 8B/10B encoding scheme. That is, the 8-bit parallel data TX [7:0] may be encoded into 10-bit parallel data. Likewise, in each the SERDES sets 10-2 to 10-N, two additional bits are required for every eight bits of data to be transmitted, which disadvantageously aggravates the transmission overload. The 10-bit parallel data may be sent to a serializer 13 such as, for example, a multiplexer. The serializer 13 may convert the parallel data into serial data based on the system clock from the clock system 16. A driver 14 such as, for example, a low-voltage differential signaling (LVDS) device, may then send differential serial data via the corresponding external channel 11-1 such as, for example, multiple wires, to a receiver 24. The receiver 24, which may include an LVDS device, converts the differential serial data into serial data. A re-sampling circuit 15 including, for example, data flip flops (DFF), may sample the serial data based on a clock signal from a phase interpolator 17. A de-serializer 23 such as a de-multiplexer may convert serial data from the re-sampling circuit 15 into 10-bit parallel data based on the clock signal from the interpolator 17. A decoder 22 such as, for example, a PRBS-format decoder, may convert the 10-bit parallel data into 8-bit parallel data RX [7:0].
The clock signal provided by the phase interpolator 17 and the clock signal provided by the CDR 18 may have the same frequency but different phases. Generally, a CDR like the CDR 18 may suffer from extreme sensitivity to clock skew between clock domains within the CDR. FIG. 1B is a schematic diagram illustrating the issue of clock skew. Referring to FIG. 1B, serial data such as DATA 1 and DATA 2 may have substantially the same frequency and phase when transmitted at a transmitter side. These serial data may be transmitted over different channels 11-1 and 11-2 and, when received at a receiver side, may have the same frequency but may be out of phase with respect to one another due to, for example, different parasitic effects generated during transmission over the different channels 11-1 and 11-2. Such a phase shift is referred to as a clock skew. Because a CDR may be required to generate recovered clock edges which are ideally located to allow registration of the incoming data at a point of maximum signal quality, given the high-speed nature of the CDR and the relatively low noise margin, even minor errors in the alignment of clock edges to data availability may result in erroneous data being captured. To alleviate the issue of clock skew, a delay locked loop (DLL) and a relatively large memory may be employed in the phase interpolator 17. The DLL may be as large as a PLL and the memory may include a great number of logic circuits, which may significantly increase the device size and hamper the miniaturization of a CDR receiver.